1. Field of the Invention
The present invention relates generally to manufacturing processes requiring lithography and more particularly to characterizing and monitoring the inter-field errors of semiconductor wafer stages.
2. Description of the Related Art
Today""s lithographic processing requires ever tighter layer-to-layer overlay tolerances to meet device performance requirements. Overlay registration is defined as the translational error that exists between features exposed layer to layer in the vertical fabrication process of semiconductor devices on silicon wafers. Other names for overlay registration include, registration error and pattern placement error, and overlay error. Overlay registration on critical layers can directly impact device performance, yield and repeatability. Increasing device densities, decreasing device feature sizes and greater overall device size conspire to make pattern overlay one of the most important performance issues during the semiconductor manufacturing process. The ability to accurately determine correctable and uncorrectable pattern placement error depends on the fundamental techniques and algorithms used to calculate lens distortion, stage error, and reticle error.
A typical microelectronic device or circuit may consist of 20-30 levels or pattern layers. The placement of pattern features on a given level must match the placement of corresponding features on other levels, i.e. overlap, within an accuracy which is some fraction of the minimum feature size or critical dimension (CD). Overlay error is typically, although not exclusively, measured with an optical overlay metrology tool. See Semiconductor Pattern Overlay, N. Sullivan, SPIE Critical Reviews Vol. CR52, 160:188; Accuracy of Overlay Measurements: Tool and Mark Asymmetry Effects, A. Starikov, et. al., Optical Engineering, 1298:1309, 1992.
Lithographers have crafted a variety of analysis techniques that attempt to separate out systematic process induced overlay error from random process induced error using a variety of statistical methods. See A Computer Aided Engineering Workstation for Registration Control, E. McFadden, C. Ausschnitt, SPIE Vol. 1087, 255:266, 1989; A xe2x80x9cGolden Standardxe2x80x9d Wafer Design for Optical Stepper Characterization, K. Kenp, C., King, W. W., C. Stager, SPIE Vol. 1464, 260:266, 1991; Matching Performance for Multiple Wafer Steppers Using an Advanced Metrology Procedure, M. Van den Brink, et. al., SPIE Vol. 921, 180:197, 1988; Characterizing Overlay Registration of Concentric 5X and 1X Stepper Exposure Fields Using Interfield Data, F. Goodwin, J. Pellegrini, SPIE Vo. 3050, 407:417, 1997; Super Sparse Overlay Sampling Plans: An Evaluation of Methods and Algorithms for Optimizing Overlay Quality Control and Metrology tool Throughout, J. Pellegrini, SPIE Vol. 3677, 72:82, 36220. The importance of overlay error and its impact to yield can be found elsewhere. See Measuring Fab Overlay Programs, R. Martin, X. Chen, I. Goldberger, SPIE Conference Metrology, Inspection, and Process Control for Microlithography XIII, 64:71, March, 1999; A New Approach to Correlating Overlay and Yield, M. Preil, J. McCormack, SPIE Conference on Metrology, Inspection, and Process Control for Microlithography XIII, 208:216, March, 1999. Lithographers have created statistical computer algorithms (for example, Klass II. See Lens Matching and Distortion testing in a multistepper, sub-micron environment, A. Yost, et al., SPIE Vol. 1087, 233:244, 1989 and Monolith; A Computer Aided Engineering Workstation for Registration Control, supra) that attempt to separate out correctable sources of pattern placement error from non-correctable sources of error. See Analysis of Overlay Distortion Patterns, J. Armitage, J. Kirk, SPIE Vol. 921, 207:221, 1988; Method to Budget and Optimize Total Device Overlay, C. Progler, et al., SPIE Vol. 3679, 193:207, 1999 and U.S. Pat. No. 5,444,538, entitled System and Method for Optimizing the Grid and Intrafield Registration of Wafer Patterns, J. Pellegrini, Aug. 22, 1995. Overall theoretical reviews of overlay modeling can be found in Semiconductor Pattern Overlay, N. Sullivan, SPIE Critical Reviews Vol. CR52, 160:188 and Machine Models and Registration, T. Zavecz, SPIE Critical Reviews Vol. CR52, 134:159.
The effects of overlay error are typically divided into the following two major categories for the purpose of quantifying overlay error and making precise exposure adjustments to correct the problem. The first category, grid or inter-field error, is the positional shift and rotation or yaw of each exposure pattern, exposure field, or simply field, with reference to the nominal center position of the wafer 2001 and 2010 in FIGS. 20A and 20B respectively.
Referring to FIG. 20A, the intra-field error in field placement on the wafer is shown as a vector offset 2002 for each field. This vector offset is the difference in the placement of the field center from its ideal or nominal position and actual position, and represents one of the components of the inter-field error, that the present invention will determine. FIG. 20B shows the other part of intra-field error, which is the yaw or rotational error in the placement of the individual fields, that is also determined by this technique.
Overlay modeling algorithms typically divide grid or inter-field error into sub-categories or components, the first five of which are translation, rotation, magnification or scale, non-orthogonality, and stage distortion. See Matching Performance for Multiple Wafer Steppers Using an Advanced Metrology Procedure, supra. The following discussion is concerned with wafer stage distortion and yaw induced registration or overlay error; these global or inter-field positional errors may be caused by the wafer stage subsystem of the stepper.
The second category, intra-field overlay error, is the positional offset of an individual point inside a projected field referenced to the nominal center of an individual exposure field, as illustrated in FIG. 20A. Here the term xe2x80x9cnominal centerxe2x80x9d means the exact location of the center of a perfectly aligned exposure field. FIG. 20A schematically shows intra-field overlay error as a set of vector displacements within the exposure field, each vector representing the magnitude and direction of the placement error. The following four main components each named for a particular effect are typically used to describe the sources of intra-field error: translation, rotation, scale or magnification, and lens distortion.
Intra-field overlay errors are typically related to lens aberrations and reticle alignment. Separation of the overlay error into inter-field and intra-field components is based on the physically distinguishable sources of these errors, lens aberrations or reticle positioning for intra-field and the wafer stage for inter-field.
It is important for this discussion to realize that most overlay measurements are made on silicon product wafers after each lithographic process, prior to final etch. Product wafers cannot be etched until the alignment attributes or overlay target patterns are properly aligned to the underlying overlay target patterns. There are many types of alignment attributes or overlay target patterns, some of which are shown in FIG. 1. Others are shown in U.S. Pat. No. 6,079,256 entitled Overlay Alignment Measurement of Wafers, N. Bareket, Jun. 27, 2000 (see FIG. 1b); Matching Management of Multiple Wafer Steppers Using a Stable Standard and a Matching Simulator, M. Van den Brink, et al., SPIE Vol. 1087, 218:232, 1989; Automated Electrical Measurements of Registration Errors in Step and Repeat Optical Lithography Systems, T. Hasan, et al., IEEE Transactions on Electron Devices, Vol. ED-27, No. 12, 2304:2312, December 1989; U.S. Pat. No. 5,757,507 entitled Method of Measuring Bias and Edge Overlay Error for Sub 0.5 Micron Ground Rules, C. Ausschnitt et al., May 26, 1998; U.S. Pat. No. 6,143,621 entitled Capacitor Circuit Structure for Determining Overlay Error, K. Tzeng, et al., Nov. 7, 2000. Manufacturing facilities rely heavily on exposure tool alignment, wafer stage matching and calibration procedures. See Stepper Matching for Optimum Line Performance, T. Dooley, Y. Yang, SPIE Vol. 3051, 426:432, 1997; Matching Management of Multiple Wafer Steppers Using a Stable Standard and a Matching Simulator, supra; Matching Performance for Multiple Wafer Steppers Using an Advanced Metrology Procedure, supra, to help insure that the stepper or scanner tools are aligning properly; inaccurate overlay modeling algorithms can corrupt the exposure tool calibration procedures and degrade the alignment accuracy of the exposure tool system. See Characterizing Overlay Registration of Concentric 5X and 1X Stepper Exposure Fields Using Interfield Data, supra.
Over the past 30 years the microelectronics industry has experienced dramatic rapid decreases in critical dimension by constantly improving lithographic imaging systems. See A New Lens for Submicron Lithography and its Consequences for Wafer Stepper Design, J. Biesterbos, et al., SPIE Vol. 633, Optical Microlithography V, 34:43, 1986; New o.54 Aperature I-Line Wafer Stepper With Field by Field Leveling Combined with Global Alignment, M. Van den Brink, B. Katz, S. Wittekoek, SPIE Vol. 1463, 709:724, 1991; Step and Scan and Step and Repeat, a Technology Comparison, M. Van den Brink, et al., SPIE Vol. 2726, 734:753; 0.7 NA DUV Step and Scan system for 150 nm Imaging with Improved Overlay, J. V. Schoot, SPIE Vol. 3679, 448:463, 1999.
Today, these photolithographic exposure tools or machines are pushed to performance limits. As the critical dimensions of semiconductor devices approach 50 nm, the overlay error requirements will soon approach atomic dimensions. See Life Beyond Mix-and-Match: Controlling Sub-0.18 micron Overlay Errors, T. Zavecz, Semiconductor International, July 2000. To meet the needs of next generation device specifications new overlay methodologies need to be developed. In particular, overlay methodologies that can accurately separate out systematic and random effects and break them into assignable cause will greatly improve device process yields. See A New Approach to Correlating Overlay and Yield, supra; Expanding Capabilities in Existing Fabs with Lithography Tool-matching, F. Goodwin et al., Solid State Technology, 97:106, June 2000; Super Sparse overlay sampling plans: An Evaluation of Methods and Algorithms for Optimizing Overlay Quality Control and Metrology Tool Throughput, supra; Lens Matching and Distortion Testing in a Multi-Stepper, Sub-Micron Environment, J. V. Schoot, SPIE Vol. 3679, 448:463; 1999; ArF Step And Scan Exposure System For 0.15 Micron and 0.13 micron Technology Node, J. Mulkens et al., SPIE Conference on Optical Microlithography XII, 506:521, March 1999. In particular, new overlay methodologies that can be implemented into advanced process control or automated control loops will be most important. See Comparisons of Six Different Intra-field Control Paradigms in an Advanced Mix and Match Environment, J. Pellegrini, SPIE Vol. 3050, 398:406, 1997; Characterizing Overlay Registration of Concentric 5X and 1X Stepper Exposure Fields Using Interfield Data, supra, U.S. Pat. No. 5,877,861 entitled Method for Overlay Control System, Auschnitt et al., Mar. 2, 1999. Finally, another area where quantifying intra-field error is of vital concern is in the production of photomasks or reticles during the electron beam manufacturing process. See Handbook of Microlithography and Microfabrication Vol. 1 P. Rai-Choudhury 1997 pg. 417.
Several common procedures are used to determine the relative magnitude of wafer stage placement error, semi-independent of other sources of registration or overlay error. Semiconductor manufacturing facilities use the resulting placement error information to manually or automatically adjust the wafer stage and stepper alignment system in such a way as to minimize the impact of overlay error. The technique has been simplified for illustration. See Matching Management of Multiple Wafer Steppers Using a Stable Standard and a Matching Simulator, supra; Matching Performance for Multiple Wafer Steppers Using an Advanced Metrology Procedure, supra. FIG. 3 shows a typical set of geometrically placed overlay target patterns consisting of a matching pair of male 302 and female 304 targets. The male 302 and female 304 targets are regularly spaced across a wafer stage test reticle 306 as shown in FIG. 3. It should be noted that the chrome target patterns on most reticles are 4 or 5 times larger as compared with the patterns they produce at the image plane; this simply means modern steppers or projection lithography tools are reduction systems. First, a photoresist coated wafer is loaded onto an exposure tool or stepper wafer stage and globally aligned. Next, the full-field image of the wafer stage test reticle is exposed several times at various positions across the surface of the photoresist coated wafer, see FIG. 22. In addition, several wafer alignment marks are also printed across the wafer using the wafer stage test reticle as shown in FIGS. 3 and 22. For purposes of illustration, we assume that the full-field of the wafer stage test reticle consists of an 11-by-11 array of male and female target pairs (separation d*M) evenly spaced at pitch pxe2x80x2*M, across the reticle surface, see FIGS. 3 and 5. The pattern is then sent through the remaining portions of the lithographic patterning process to delineate the resist pattern.
Depending on the technique used for stage matching, the resulting pattern can be permanently etched into a thin film or substrate if so desired. The final sequence of stage matching involves transferring the patterned wafer and wafer stage test reticle into a different exposure tool or stepper and recording alignment coordinates in the following way. The patterned wafer is globally and finely aligned into position using the previously placed wafer alignment marks, as shown in FIG. 22. Next, the wafer stage is moved around in such a way as to align the wafer stage test reticle containing an 11-by-11 array of male targets directly on a field exposure pattern (or field) containing an 11-by-11 array of female target patterns, see FIGS. 4 and 22. This involves shifting the wafer the small increment d, illustrated in FIGS. 5 and 6, so male and female targets lie on top of one another, as shown in FIG. 4.
When the stepper has finished the alignment procedure, the x, y wafer stage coordinates and overlay error associated with several male-female target pairs are electronically recorded. This step, align, and record procedure is repeated across the entire wafer for each exposure field containing the 11-by-11 target array, illustrated in FIGS. 23 and 24. The electronically recorded target coordinates and overlay errors are then entered into a statistical modeling algorithm that calculates the components of inter-field and intra-field overlay error.
An important point is that the resulting inter-field or wafer stage overlay error does not yield the unique overlay error of the wafer stage in question; instead, it only can be used to report the inter-field or wafer stage overlay error as referenced to another machine stage, sometimes called a xe2x80x9cmotherxe2x80x9d or xe2x80x9creference machinexe2x80x9d. In general, semiconductor manufacturers rely on some kind of stage matching or cross-referencing technique to calculate the relative wafer stage overlay error.
There are several problems associated with this technique. First, as noted above, the technique does not yield the unique wafer stage overlay error; it only provides a relative measure of all components. To obtain the relative stage error between two machines, the inter-field errors so determined must be subtracted from one another, which results in increasing the noise in the determination of stage error. In some cases semiconductor manufacturing facilities (fabs) produce a special xe2x80x9cgoldenxe2x80x9d reference wafer that can be used for comparison purposes.
Second, the models used to calculate the systematic inter-field error usually do not account for the stage error associated with distortion and yaw. They are typically limited to translation, rotation, orthogonality and x and y scale errors. See A Computer Aided Engineering Workstation for Registration Control, supra. Higher order errors are ignored or otherwise not taken into account. By relying on wafers created on a reference machine, these wafers are not identical or have unknown overlay deviations from one another since they must be exposed on a single machine in a short time to minimize machine instabilities. See Matching Management of Multiple Wafer Steppers Using a Stable Standard and a Matching Simulator, supra. It would be very desirable to have an inter-field overlay technique that would calculate the wafer stage component of overlay error independently from a reference exposure tool or golden wafer without the need for matching to another machine""s stage. See Mix-And-Match: A necessary Choice, R. DeJule, Semiconductor International, 66:76, February 2000.
Another technique (See Matching Performance for Multiple Wafer Steppers Using an Advanced Metrology Procedure, supra; Expanding Capabilities in Existing Fabs with Lithography Tool-matching, supra) utilizes a reference machine (projection imaging tool) for measurement of inter-field overlay error. The reference machine is typically one that is closest to the average of all machines in the factory (See Expanding Capabilities in Existing Fabs with Lithography Tool-Matching, supra) or a machine that exhibits long term stability. See Matching Performance for Multiple Wafer Steppers Using an Advanced Metrology Procedure, supra. On the reference machine, a reference wafer is exposed, developed and etched. The reference wafer is exposed using an inner box reticle, 3302 in FIG. 33, that contains a regular array of inner box structures 3304 in a regular pattern covering the wafer. A 3xc3x973 array is shown in FIG. 34.
Next, wafer alignment marks 3202 are exposed using a designated portion of the inner box reticle or a separate reticle containing the wafer alignment mark, as shown in FIG. 32. The reference wafer is then typically etched and stripped to produce pits 3502 in FIG. 35, corresponding to the inner box locations. A number of such wafers are produced and the locations of the inner box arrays (individual printings of the inner box reticle) then represent the inter-field positions of the reference machine.
Next, a reticle containing outer box structures, 3602 in FIG. 36 and detailed in FIG. 37, in the same nominal positions as the inner box reticle (or the pattern required to produce a completed, machine readable alignment attribute), is placed on the machine to be measured. A completed reference wafer shown in FIG. 34 is coated with photoresist, exposed and developed. The result is a developed reference wafer illustrated in FIG. 38 and detailed in FIG. 39, containing box-in-box structures that can then be measured on an overlay metrology tool. The resulting measurements are then typically averaged over each field in FIG. 38, and the twenty-five measurements within each field are averaged together to produce a net translation (Dxg, Dyg) and rotation (Yawg) for each of the nine fields. This averaged data is then fit to the following set of equations. See Matching of Multiple Wafer Steppers for 0.35 micron Lithography Using Advanced Optimization Schemes, M. Van den Brink, et al. SPIE Vol. 1926, 188:207, 1993; Matching Performance for Multiple Wafer Steppers Using an Advanced Metrology Procedure, supra:
Dxg=Txg+sxg*xg+(xe2x88x92qg+qog)*yg+D2x*yg2+Rwxxe2x80x83xe2x80x83(eq 3) 
Dyg=Tyg+syg*yg+qg*yg+D2y*xg2+Rwyxe2x80x83xe2x80x83(eq 4) 
Yawg=Qg+syawg*ygxe2x88x922*D2y*xg+RwYxe2x80x83xe2x80x83(eq 5) 
Where:
Dxg, Dyg, Yawg=x,y,yaw grid errors at grid position xg, yg
xg, yg=grid position=position on wafer of field center with respect to the center of stage travel
Txg, Tyg=x,y grid translation
sxg, syg=x,y grid scale or magnification error
qg, qog=grid rotation, orthogonality
D2x, D2y=x,y stage bow terms
Rwx, Rwy, RwY=grid residual in the x, y, Yaw direction (we do not try fitting to these parameters).
The yaw error (Yawg) is the deviation of the rotation of the grid at a specific point. It results in a difference in field to field rotation as a function of placement position (xg, yg) on the wafer. The 10 unknown parameters (Txg, Tyg, . . . D2x, D2y) in equations 3,4,5 are solved for using standard least squares techniques. See Numerical Recipes, The Art of Scientific Computing, W. Press, et al., Cambridge University Press, 509:520, 1990.
Problems with this technique are: the systematic (repeatable) and random grid errors on the reference machine (the machine used for creating the reference wafers) are permanently recorded as half (inner or outer box) of our factory wide metrology standard. The magnitude and distribution of these errors is entirely unknown. For machine to machine comparisons of grid errors, the systematic or repeatable parts of the errors cancel out, but the influence of the random or non-repeatable error remains. This is why multiple reference wafers are typically used to improve machine to machine matching results. See Matching Management of Multiple Wafer Steppers Using a Stable Standard and a Matching Simulator, supra. Furthermore, reference machine instabilities over time lead to a drift or error in the factory wide standard represented by the reference machine. Yet another problem with this technique is that because it utilizes full size projected fields to determine the inter-field errors, it does not work with partially exposed fields as illustrated in FIG. 44. The ability to include partially exposed fields is important since product wafers typically contain multiple die within an exposure field, and therefore the inter-field error of partially exposed fields is important since it directly affects the edge die overlay error.
Another technique for grid error determination utilizing self-calibration is discussed in Self-calibration in Two-Dimensions: The Experiment, M. Takac, J. Ye, M. Raugh, R. Pease, C. Berglund, G. Owen, SPIE Vol. 2725, 130:146, 1996; Error Estimation for Lattice Methods of Stage Self-calibration, M. Raugh, SPIE. Vol. 3050, 614:625, 1997. It consists of placing a plate (artifact) with a rectangular array of measurable targets on a tool stage and measuring the absolute positions of the targets using the tool""s stage and the tool""s image acquisition or alignment system. This measurement process is repeated by reinserting the artifact on the stage but shifted by one target spacing in the X direction, then repeated again with the artifact inserted on the stage shifted by one target spacing in the Y direction. Finally, the artifact is inserted at 90 degrees relative to its initial orientation and the target positions measured. The resulting tool measurements are a set of (x, y) absolute positions in the tool""s nominal coordinate system.
Using the technique described in Self-calibration in Two-Dimensions: The Experiment, supra; and Error Estimation for Lattice Methods of Stage Self-calibration, supra, the absolute position of both targets on the artifact and a mixture of the repeatable and non-repeatable parts of the stage x,y grid error are then determined to within a global translation (Txg, Tyg), rotation (qg) and overall scale ((sxg+syg)/2) factor. Unfortunately, this technique cannot be applied to photolithographic exposure tools (machines) since the wafer position (artifact) typically cannot be placed on the wafer chuck in a position significantly (xe2x89xa71 mm) shifted from the nominal position. In some machines, such a shift may be possible with extraordinary effort on the part of the maintenance engineer, but such a procedure is completely unsuitable in ordinary production use. Wafers (artifacts) can typically be automatically reinserted on the wafer chuck rotated 90 degrees from nominal, but without the additional X or Y shifts described above, the resulting reconstructed grid errors are missing all of the 4-fold symmetric grid distortions. See Self-calibration in Two-Dimensions: The Experiment, supra; Error Estimation for Lattice Methods of Stage Self-calibration, supra. Another disadvantage of this technique is that it does not measure the stage yaw. While this is not necessary for absolute metrology tools that measure target positions over relatively small optical fields ( less than 0.5 mm) such as the Nikon 5I (See Measuring System XY-5i, K. Kodama, et. al., SPIE Vol. 2439, 144:155, 1995 or the Leica LMS IPRO Brochure, Leica), it is absolutely essential for production machines running at large projection fields ( greater than 10 mm) such as the Nikon 5205. See Nikon Lithography Tool Brochures (Japanese), Nikon. Yet another disadvantage of the aforementioned technique is that the measurement process utilizes the production machine itself to perform the metrology; this means there is less time available for making product on that machine. Yet another disadvantage of this technique is it does not allow us to measure stage error for partially exposed fields.
Therefore, there is a need for overlay metrology tool to determine wafer stage positional errors. In addition, there is a need to measure the wafer stage positioned error in a production environment by the day to day operating personnel. There is also a need to determine the inter-field error of partially exposed fields.
A wafer stage error map is created using standard overlay targets and a special numerical algorithm. A reticle consisting of a 2-dimensional array of standard overlay targets is exposed several times onto a photoresist coated silicon wafer using a photolithographic projection tool (machine). Next, the overlay targets are measured for placement error using a conventional overlay metrology tool. The resulting overlay error data are then fed into a software program that generates a 2-dimensional wafer stage error map. Most importantly, the method determines wafer stage overlay error, namely, wafer stage distortion and yaw, excluding, total or average translation, and rotation. In summary, the projected field of the overlay reticle is used as a rigid 2-dimensional ruler, and the stage errors are determined in detail with respect to the dimensions of a single projected image field. The method described above does not require the use of a special reference stepper or golden wafer to obtain the wafer stage contributions to placement error. The preferred embodiment is both self-consistent and self-referenced thus reducing the need of cross calibration between different exposure tool sets to a bare minimum. In addition, variations of the preferred embodiment can be used to calculate stage repeatability or precision using standard statistical methods. The ability to determine true stage distortion and yaw without cross calibration or reference to other stepper systems allows the user to more accurately model additional sources of placement error. The method described above can be adjusted for accuracy by simply adjusting the number of measurements made of the alignment attributes or overlay targets. The invention requires exposing and printing an array of fields in a periodic interlocking pattern across the wafer. Next, the resulting overlay target patterns can be measured for overlay error using a standard commercially available optical overlay metrology tool. Next, the distortion and yaw components of stage overlay error are computed using a special algorithm. The method and apparatus form a methodology that can be modified slightly to achieve varying degrees of overall accuracy. The following procedure can be easily implemented in a modern semiconductor manufacturing facility.
A reticle containing special overlay target patterns, for example, see FIG. 21A, is placed into a projection imaging tool or machine, as shown in FIG. 19, where the term lithographic exposure tool includes contact or proximity printers, steppers, scanners, direct write, e-beam, x-ray, SCALPEL, IPL, or EUV machines. See Direct-referencing Automatic Two-Points Reticle-to-Wafer Alignment Using a Projection Column Servo System; M. Van den Brink, H. Linders, S. Wittekoek, SPIE Vol 633, Optical Microlithography V, 60:71, 1986; New o.54 Aperture I-Line Wafer Stepper with Field by Field Leveling Combined with Global Alignment, M. Van den Brink et al., SPIE Vol. 1463, 709:724, 1991; U.S. Pat. No. 4,861,146, entitled Variable Focal Lens Device, Hatase et al., Aug. 29, 1989. Micrascan((trademark)) III Performance of a Third Generation, Catadioptric Step and Scan Lithographic Tool, D. Cote, et. al., SPIE. Vol. 3051, 806:816, 1997; ArF Step And Scan Exposure System For 0.15 Micron and 0.13 micron Technology Node, supra; 0.7 NA DUV Step and Scan System for 150 nm Imaging with Improved Overlay, supra; Optical Lithographyxe2x80x94Thirty Years and Three Orders of Magnitude, J. Bruning, SPIE Vol. 3051, 14:27, 1997; Large Area Fine Line Patterning By Scanning Projection Lithography, H. Muller, et. al., MCM 1994 Proceedings, 100:104; U.S. Pat. No. 5,285,236 entitled Large-area, High-throughput, High-Resolution Projection Imaging System, K. Jain, Feb. 8, 1994; Development of XUV Projection Lithography at 60-80 nm, B. Newnam, et. al., SPIE vol. 1671, 419:436, 1992; Mix-And-Match: A necessary Choice, supra; Optical Lithographyxe2x80x94Thirty Years and Three Orders of Magnitude, supra. Next, a photoresist coated wafer is loaded onto the machine; fine wafer alignment is unnecessary.
A series of projection field exposures each containing a sub-array of overlay target patterns is exposed onto the photoresist coated wafers in a partially overlapping interlocking pattern as illustrated in FIGS. 13, 14A, 14B, and 26. Each projection field exposure is separated from the previous exposure by a distance such that neighboring fields will have the inner or outer boxes closest to their perimeters interlocking from one field to another, as shown in FIG. 14B. After the final exposure the wafer is removed from the machine and sent through the final resist development steps.
The resulting resist relief overlay target patterns are then measured for registration, placement or overlay error using an overlay metrology tool such as a KLA-Tencor model 5100, or 5105. See KLA 5105 Overlay Brochure, KLA-Tencor; KLA 5200 Overlay Brochure, KLA-Tencor, Quaestor Q7; Quaestor Q7 Brochure, Bio-rad Semiconductor Systems, or other. See U.S. Pat. No. 5,438,413 entitled Process for Measuring Overlay Misregistration during Semiconductor Wafer Fabrication, Mazor et al., Aug. 1, 1995; U.S. Pat. No. 6,079,256, supra. The resulting data set is entered into a computer algorithm for analysis and the overlay components associated with wafer stage distortion and stage yaw are calculated. If desired, the resulting data can be displayed visually.
The fact that the preferred method utilizes a high precision overlay metrology tool for local measurements and extracts the overlay error associated with wafer stage distortion and yaw in a unique way means that the technique is readily employed in semiconductor manufacturing facilities (fabs). In addition, this invention can be used in conjunction with traditional overlay techniques to better understand, model and correct pattern placement errors. Additional applications of the above outlined procedure include: improved lithographic simulation using conventional optical modeling software, advanced process control in the form of feedback loops that automatically adjust the wafer stage for optimum performance, and finally, wafer stage correction algorithms that compensate for distortion and yaw effects. The software algorithm and apparatus form a self-referenced methodology that does not require a special set of overlay calibration wafers, a special reference stepper tool or assumptions concerning the magnitude of distortion and yaw overlay errors.